There is a special class of logic gates, called universal gates, any one of which is sufficient to express any desired computation. The NAND gate is truly global, given that it is already known, each Boolean function can be represented in a circuit that contains only NOT and AND gates, it is sufficient to show that these gates can be defined from the NAND gate. The effect of Rashba spin-orbit interaction (SOI) on the gate response and spin current density in a series of non-interacting one-dimensional rings connected to some leads is studied theoretically within the waveguide theory. The gates response and spin current density are computed in geometry of the system containing two terminal double quantum rings. Also, the presence and absence of Rashba SOI are treated as the two inputs of the AND/NAND/NOT gates. Furthermore, simulation of the device performance demonstrates that vital improvement toward spintronic applications can be achieved by optimizing device parameters such as magnetic flux and Rashba coefficient.
In Integrated Circuit (IC) Technology practical circuit application of single electron devices is impossible due to it poor driving capability according to this point it is essential to accept implementation of new methodology such as hybridization of single electron transistor (SET) and complementary metal oxide semiconductor (CMOS) device interface circuit. This hybrid SETMOS is operated in room temperature. Further with the help of science and technology, it is easy to communicate with people all over the world, within a minute by sharing large amount of information through messages and email. So it is essential to study the fastest communication in analog and digital media. High speed computing technological faces lots of problems so it is essential to think different pathway to improve communication performance in the future. Generally basic communication system includes encoder and decoder to convert and convey the information in different pathway. In this paper we proposed basic building blocks of communication system using Multiple Valued logic (MVL). Herein binary to quaternary encoder is implemented by using NAND and NOR gate. Quaternary to binary decoder is proposed by using literal and universal literal gate. MIB model of SET is calibrated with conventional BSIM 4.6.1 MOSFET 45nm model. All circuits are simulated and validated in T-spice pro environment. The proposed NAND and NOR gate consumes 2050nw and 42ps delay while literal and universal literal gate consume 1050nw and 41ps delay in comparison to CMOS counterparts.
universal nand gate pdf download
NAND & NOR gates are called as universal gates. Because we can implement any Boolean function, which is in sum of products form by using NAND gates alone. Similarly, we can implement any Boolean function, which is in product of sums form by using NOR gates alone. 2ff7e9595c
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